S25FL128LAGMFI010 Flash Memory Chips 8-SOIC Package 128 MbFL-L Flash Floating Gate technology

S25FL128LAGMFI010 Flash Memory Chips 8-SOIC Package 128 MbFL-L Flash Floating Gate technology

General description

The FL-L Family devices are Flash non-volatile memory products using:

• Floating Gate technology

• 65-nm process lithography

The FL-L family connects to a host system via a serial peripheral interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are double data rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.

The architecture features a page programming buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.

By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.